Functional test generation for non-scan sequential circuits

The feasibility of generating high quality functional test vectors f o r sequential circuits using the Growth (G) and Disappearance ( 0 ) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model b y proving the ability of this model t o guarantee complete stuck fault coverage an combinational and sequential circuits synthesized employing algebraic transformations. W e also provide experimental results o n a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the ef ic iency and limitation of the functional approach.